MEMORY SHARING TYPE MULTIPROCESSOR SYSTEM
PROBLEM TO BE SOLVED: To prevent the processing efficiency from decreasing owing to an overload on a system bus by connecting two CPU clusters by a fast cache bus and managing the state of a cache memory by a global cache. SOLUTION: Two CPU clusters 10 and 20 equipped with CPUs having write- back ty...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | PROBLEM TO BE SOLVED: To prevent the processing efficiency from decreasing owing to an overload on a system bus by connecting two CPU clusters by a fast cache bus and managing the state of a cache memory by a global cache. SOLUTION: Two CPU clusters 10 and 20 equipped with CPUs having write- back type cache memories, I/O clusters 30 and 40, and a main memory 50 are connected by the system bus 60, the CPU clusters 10 and 20 are connected to each other by the cache bus 80, and the global cache 70 is connected to the cache bus 80. The cache bus 80 is a fast bus and used only for data transmission and reception between the CPU clusters 10 and 20 and data control by the global cache 70. The system bus 60 is not used for coherency control over the cache memories of the respective CPUs and the data transfer between the CPU clusters 10 and 20, so the use efficiency of the system bus can be improved. |
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