STRUCTURE OF INSTRUCTION WORD, INSTRUCTION WORD PROCESSING METHOD AND INSTRUCTION DECODER

PROBLEM TO BE SOLVED: To execute an instruction by minimum branches while reducing a ROM capacity. SOLUTION: An instruction word is separated into the address calculation and the main processing of the instruction word for transfer and calculation. Address registers 26 to 28 of a number required by...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: TSUKAMOTO AKITO
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To execute an instruction by minimum branches while reducing a ROM capacity. SOLUTION: An instruction word is separated into the address calculation and the main processing of the instruction word for transfer and calculation. Address registers 26 to 28 of a number required by the instruction word are prepared to use a micro-code executing only the address calculation. Then, required address values are all prepared before the main processing of the instruction word by the micro-code corresponding to each addressing mode, after then, it is branched to a micro-code executing the main processing of the instruction word. In the case of an instruction word added with an addressing mode and requiring the calculation of the address value, an instruction decoder directly designate a microcode executing only the address calculation, but when it is not such an instruction, the instruction decoder designates the micro-code executing the main processing of the instruction word by a starting address ROM 8.