SELF-MATCHING CONTACT POINT PROCESS IN SEMICONDUCTOR MANUFACTURE, IMPROVING METHOD FOR STANDARD SELF- MATCHING CONTACT POINT SEMICONDUCTOR MANUFACTURE PROCESS AND SELF-MATCHING CONTACT POINT SEMICONDUCTOR MANUFACTURE

PROBLEM TO BE SOLVED: To reduce the possibility of an electric fail in a semiconductor device by depositing an insulating layer on a gate stack formed in manufacture, etching the insulating layer, and forming a spacer which insulates/separates the gate stack from a contact point area. SOLUTION: The...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: WITTMANN JUERGEN, DOBUZINSKY DAVE, WOLFGANG BERGNER, BRUNO SPULER
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To reduce the possibility of an electric fail in a semiconductor device by depositing an insulating layer on a gate stack formed in manufacture, etching the insulating layer, and forming a spacer which insulates/separates the gate stack from a contact point area. SOLUTION: The spacer layer of nitride, oxide or oxide/nitride is deposited after a CB (bit line contact point) nitride liner is etched and it is operated as an insulating layer. The spacer layer of insulating nitride, oxide or oxide/ nitride is etched and it is sufficiently insulated from a transistor element. It becomes a contact point with a diffusion area and inhibits the opening of CB. The gate stack forming process of an SAC process is executed on a gate oxide layer in a usual way. SiN or SiON is deposited on a gate stack and BPSG and TEOS are continuously deposited. Then, chemical/mechanical polishing is executed after BPSG is deposited and before TEOS is deposited.