SEMICONDUCTOR WAFER, AND METHOD FOR INSPECTING SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a wafer to be inspected together with a method for wafer level burn-in test using it, wherein with the supply of a voltage to a defective chip being limited, a normal wafer level burn-in test is conducted with other satisfactory chips. SOLUTION: A power source pad 3,...

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Bibliographische Detailangaben
Hauptverfasser:	SUGIMOTO HIROMITSU, YAMAMOTO SHIGEHISA
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS SEMICONDUCTOR DEVICES TESTING
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Beschreibung
Zusammenfassung:	PROBLEM TO BE SOLVED: To provide a wafer to be inspected together with a method for wafer level burn-in test using it, wherein with the supply of a voltage to a defective chip being limited, a normal wafer level burn-in test is conducted with other satisfactory chips. SOLUTION: A power source pad 3, a GND pad 4, and a voltage pad 5 are formed on a chip 2. The surface area of the voltage pad 5 is larger than that of the power source pad 3. The power source pad 3 and the voltage pad 5 are connected to each other through a fuse 6. A chip which is decided as being defective by a wafer test in advance among the all the tips 2, the fuse 6 of the chip 2 is disconnected by electric fusion or laser irradiation.