NEGATIVE BOOSTING CIRCUIT

PROBLEM TO BE SOLVED: To provide a negative boosting circuit which restrains the leakage and the substrate bias effect of a parasitic bipolar transistor and whose efficiency is good at a low voltage while the negative boosting circuit is constituted by using an N-channel MOS transistor. SOLUTION: Wh...

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1. Verfasser: ARIGA RIE
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To provide a negative boosting circuit which restrains the leakage and the substrate bias effect of a parasitic bipolar transistor and whose efficiency is good at a low voltage while the negative boosting circuit is constituted by using an N-channel MOS transistor. SOLUTION: When a negative boosting circuit is constituted by using N- channel MOS transistors 81 to 88 in a tripple well process, the substrate potential of the N-channel MOS transistors 81 to 88 is made to float. Thereby, a rise in the threshold of the transistors 81 to 88 due to a substrate bias effect is suppressed, and the collector current of a parasitic NPN transistor due to a forward current from a substrate caused by a boosting operation is suppressed. In addition, when the potential of a PW substrate in the start of the boosting operation is set at a ground potential by P-type MOS transistors 111 to 118, the substrate bias effect of the N-channel MOS transistors 81 to 88 is eliminated, and a boosting operation at 2 V or lower can be performed.