SISTEMA PER IL TRASFERIMENTO RAPIDO DI DATI

The memory controller (104) for managing data within a memory component (200) includes a data manager (304) and a buffer memory (302). The data manager (304) has a compression/decompression engine (400), a number of data outputs connected to the memory (106), and a number of control outputs connected to the memory (106). The memory controller (104) for managing data within a memory component (200) includes a data controller (300) with parallel outputs. A buffer memory (302) has parallel inputs and parallel outputs, the inputs being connected to the data controller (300). A data manager (304) is connected to the parallel outputs of the buffer memory (302). The data manager (304) has a compression/decompression engine (400), a number of data outputs connected to the memory (106), and a number of control outputs connected to the memory (106). The memory controller (104) includes further program circuits (306) connected to the data controller (300), the buffer memory (302) and the data manager (304). The memory itself (106) comprises several banks of memory, each of which comprise atomic resolution storage (ARS) devices.