DISPOSITIVO DI MEMORIA A SEMICONDUTTORE E PROCEDIMENTO PER LA SUA FABBRICAZIONE

PURPOSE:To prevent edges of a chip from being broken when the chip is subjected to a dicing by the use of a silicon wafer, wherein the main surface of the silicon wafer is a {100} plane and four peripheral side surfaces of the same are {110} planes, so that a thin capacitor can have four peripheral...

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1. Verfasser: YASUE TAKAO
Format: Patent
Sprache:ita
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Zusammenfassung:PURPOSE:To prevent edges of a chip from being broken when the chip is subjected to a dicing by the use of a silicon wafer, wherein the main surface of the silicon wafer is a {100} plane and four peripheral side surfaces of the same are {110} planes, so that a thin capacitor can have four peripheral inner {100} planes, whereby the thickness of an oxide film at a capacitor can be rendered uniform. CONSTITUTION:The surface orientation of a silicon wafer 1 is defined such that a main surface 1a thereof is in a {100} plane, and an orientation flat 1b thereof is in a {110} plane. The silicon wafer is subjected to dicing along dicing lines 2a which are parallel to the orientation flat 1b and another dicing lines 2b which are at right angles to the orientation flat 1b. Accordingly, all four peripheral side surfaces 3a, 3b, 3c and 3d of a semiconductor chip 3 have the surface orientation of a {110} plane. In addition, all four peripheral inner surfaces 7a, 7b, 7c, 7d and a bottom surface 7e of a thin capacitor 7 are set to the surface orientation of a {100} plane. Moreover, crossover lines between the dicing lines 2a and 2b, a {111} plane, and the main surface 1a are parallel to each other.