SISTEMA DI ELABORAZIONE DATI

SISTEMA DI ELABORAZIONE DATI

The multiprocessor system is based upon individual processors that have an arithmetic logic unit (5), control unit (6), high speed memory (7) that is structured as an instruction counter, index register and buffer store. An interface unit (8) connects with a processor status register (9). Access to...

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Hauptverfasser: EDUARD EVGENIEVICH IVANO, JURY EGOROVICH CHICHERIN, VYACHESLAV VIKTOROVICH TELENKOV, VALERY LEONIDOVICH DSHKHUNIAN, PAVEL ROMANOVICH MASHEVICH, SERGEI SAVVICH KOVALENKO, ALEXEI ALEXEEVICH RYZHOV
Format: Patent
Sprache:ita
Schlagworte:
CALCULATING
COMPUTING
COUNTING
HANDLING RECORD CARRIERS
PHYSICS
PRESENTATION OF DATA
RECOGNITION OF DATA
RECORD CARRIERS
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creator EDUARD EVGENIEVICH IVANO
JURY EGOROVICH CHICHERIN
VYACHESLAV VIKTOROVICH TELENKOV
VALERY LEONIDOVICH DSHKHUNIAN
PAVEL ROMANOVICH MASHEVICH
SERGEI SAVVICH KOVALENKO
ALEXEI ALEXEEVICH RYZHOV
description The multiprocessor system is based upon individual processors that have an arithmetic logic unit (5), control unit (6), high speed memory (7) that is structured as an instruction counter, index register and buffer store. An interface unit (8) connects with a processor status register (9). Access to each processor is effected by an address interrupt unit (15) that is coupled to the data address and control bus (4). Internally all modules are interconnected by a separate bus. One output of the address interrupt unit is tied to the internal bus and another is coupled to the control unit. A number of processor may be interconnected via the external bus.
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subjects CALCULATING
COMPUTING
COUNTING
HANDLING RECORD CARRIERS
PHYSICS
PRESENTATION OF DATA
RECOGNITION OF DATA
RECORD CARRIERS
title SISTEMA DI ELABORAZIONE DATI
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