SISTEMA DI ELABORAZIONE DATI

The multiprocessor system is based upon individual processors that have an arithmetic logic unit (5), control unit (6), high speed memory (7) that is structured as an instruction counter, index register and buffer store. An interface unit (8) connects with a processor status register (9). Access to each processor is effected by an address interrupt unit (15) that is coupled to the data address and control bus (4). Internally all modules are interconnected by a separate bus. One output of the address interrupt unit is tied to the internal bus and another is coupled to the control unit. A number of processor may be interconnected via the external bus.