MICROPOCESSORE PERFEZIONATO

A storage address link register system for enabling nested program branching wherein a first subroutine may call a second subroutine which is executed before the first subroutine returns program control back to the program which called it. The system includes a mechanism whereby the same set of storage address link registers may be used for nested branching both during the execution of a normal program and during the execution of an interrupt service program which breaks into the normal program and takes over control of the processor for a short interval of time. A mechanism is provided for saving the normal program values in the link registers at the commencement of the interrupt service program. A further mechanism is provided for monitoring the usage of the link registers by the interrupt program for enabling the normal program values to be restored in the link registers only after all interrupt program values have been removed from such link registers.