TRANSISTORE MOS INTEGRATO CON DISABILITAZIONE SELETTIVA DELLE SUE CELLE

TRANSISTORE MOS INTEGRATO CON DISABILITAZIONE SELETTIVA DELLE SUE CELLE

An integrated device (100) is proposed comprising at least one MOS transistor (105) having a plurality of cells (135,150). In each of one or more of the cells (135,150) a disabling structure (175,180) is provided; the disabling structure (175,180) is configured to be in a non-conductive condition wh...

Ausführliche Beschreibung

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Bibliographische Detailangaben
1. Verfasser: PATTI, Davide Giuseppe
Format: Patent
Sprache:ita
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:An integrated device (100) is proposed comprising at least one MOS transistor (105) having a plurality of cells (135,150). In each of one or more of the cells (135,150) a disabling structure (175,180) is provided; the disabling structure (175,180) is configured to be in a non-conductive condition when the MOS transistor (105) is switched on in response to a control voltage comprised between a threshold voltage of the MOS transistor (105) and an intervention voltage of the disabling structure (175,180), or to be in a conductive condition otherwise. A system (400) comprising at least one integrated device (100) as above is also proposed. Moreover, a corresponding process for manufacturing this integrated device (100) is proposed.