CIRCUITO DI PRECARICO DI BUFFER D'USCITA PER MEMORIA RAM DINAMICA

An output buffer precharge circuit for DRAM (dynamic random access memory) cells includes a latch, control circuits, an output buffer, and a precharge pulse generating section. The circuit further includes a data transition signal genrating section consisting of MOS (metal-oxide semiconductor) transistors, latches connected to the MOS transistors, inverters and NAND gates for receiving the control precharge pulse from the precharge pulse generating section; and a precharge section consisting of MOS transistors, the gates of which receive the outputs of the data transition signal generating section. Noise can be decreased during the transition from the CMOS level to the TTL (transistor-transition-logic) level, and valid data are charged or discharged in advance so that processing speed can be increased.