TRANSISTORE AD EFFETTO DI CAMPO SUPERFICIALE CON REGIONE DI SOURCE E/O DI DRAIN SCAVATE PER DISPOSITIVI ULSI

A surface field effect integrated transistor has the surface of the silicon in the source and drain areas (4, 4', 7, 7') lowered by 50-500 nm in respect to the surface of the silicon (2) underneath the gate electrode (1) by etching the silicon substrate before forming the source and drain junctions. The transistor is sturdy and reliable because of the backing-off of the multiplication zone of the charge carriers from the gate oxide by a distance greater than several times the mean free path of hot carriers, thus markedly reducing the number of hot carriers available for injection in the gate oxide. The modified fabrication steps are readily integrable in a normal CMOS fabrication process.