UNITA LOGICO ARITMETICA IN TECNOLOGIA C MOS
The arithmetic-logic unit comprises elementary cells performing logic addition, one per each pair of operand bits, which are particularly optimized as far as carry propagation speed is concerned and are controlled by an auxiliary fast logic allowing their performances to be extended to the other ope...
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| Zusammenfassung: | The arithmetic-logic unit comprises elementary cells performing logic addition, one per each pair of operand bits, which are particularly optimized as far as carry propagation speed is concerned and are controlled by an auxiliary fast logic allowing their performances to be extended to the other operations; the unit further comprises a control signal generating circuit, subdivided into a first part (DEC1), near the elementary cell of least significant position, which generates an operation selecting signal for all the cells, and into a second part (DEC2), near the elementary cell of most significant position, which generates control signals for the auxiliary logic of each elementary cell. |
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