CIRCUITO D'INTERFACCIA DI CANALE DI CONTROLLO,IN PARTICOLARE PER UN SISTEMA DI COMUNICAZIONE A PIU' PROCESSORI DISTRIBUITI

There is disclosed a control channel interface circuit for interfacing a port processor of a distributed multiprocessor communication system to a common time division multiplexed bus. The detection, extraction and synchronization of control messages passed between a central processor and port processor via a TDM bus are handled by the interface unit thereby relieving a port processor of this burden. A group of control time slots within a system frame are dedicated for the transfer of control messages between port processors and a central processor. The interface unit also monitors the operability of a respective port processor and automatically disables a faulty processor.