METHOD AND APPARATUS FOR SAVING PROCESSOR INFORMATION PRIOR TO A RESET FOR POST RESET EVALUATION

A processor reset control circuit is configured to automatically capture a prereset value of processor information stored in one or more hardware registers as part of a reset operation state machine and prior to changing the processor information to its architecturally required post reset value. Such pre reset processor information includes for example one or more pre reset values of the processor program counter (PC) and one or more pre reset values of an operating state mode register both of which may be captured in one or more pre reset capture storage devices which are then made available for evaluation purposes. Such pre reset capture storage devices store pre reset information in response to the reset and maintain the stored pre reset information until another reset occurs.