INTEGRATED CIRCUIT PACKAGE HAVING OFFSET VIAS

INTEGRATED CIRCUIT PACKAGE HAVING OFFSET VIAS

Integrated circuit packages comprise vias each of which extends from a pad in communication with an integrated circuit on a semiconductor chip through insulating material overlying the semiconductor chip to an attachment surface facing a substrate. The portion of each via proximate the attachment su...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: SU MICHAEL ZHUOYING, LEI FU, KUECHENMEISTER FRANK
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:Integrated circuit packages comprise vias each of which extends from a pad in communication with an integrated circuit on a semiconductor chip through insulating material overlying the semiconductor chip to an attachment surface facing a substrate. The portion of each via proximate the attachment surface is laterally offset from the portion proximate the pad from which it extends in a direction away from the centre of the semiconductor chip. Metallic material received in the vias mechanically and electrically interconnects the semiconductor chip to the substrate.