Semiconductor memory device

In a semiconductor memory device (1), voltage application from a memory gate electrode (G) of the memory capacitor (4) to a word line can be blocked by a rectifier element (3) depending on values of voltages applied to the memory gate electrode (G) and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device (1), for example, each bit line contact (BC15) is shared by four anti-fuse memories (2a 6 , 2a 7 , 2a 10 , and 2a 11 ) adjacent to each other and each word line contact (WC12) is shared by four anti-fuse memories (2a 3 , 2a 4 , 2a 7 , and 2a 8 ) adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.