An address generation unit

An address generation unit

An AGU (3) has a Register File (4) providing order (R), stage (S), and displacement (N) values to a DAU (5) for performing one of eight addressing operations. The Register File provides the input (X) and receives the output (Y). Within the DAU (5) selection multiplexers (13,14) select full adder out...

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Hauptverfasser: CHRISTOPHER BLEAKLEY, BRIAN MURRAY, VINCENT BERG, JOSE RODIGUEZ
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator CHRISTOPHER BLEAKLEY
BRIAN MURRAY
VINCENT BERG
JOSE RODIGUEZ
description An AGU (3) has a Register File (4) providing order (R), stage (S), and displacement (N) values to a DAU (5) for performing one of eight addressing operations. The Register File provides the input (X) and receives the output (Y). Within the DAU (5) selection multiplexers (13,14) select full adder outputs to provide Y, or bit-select from adders and the input (X) to provide Y. For a radix-4 operation, MSBs are taken from the input (X), middle bits are taken from the output of a first adder (adder1), and the LSBs are taken from the output of a second adder (adder2) if there is a carry out from the first adder.
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title An address generation unit
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