An address generation unit

An AGU (3) has a Register File (4) providing order (R), stage (S), and displacement (N) values to a DAU (5) for performing one of eight addressing operations. The Register File provides the input (X) and receives the output (Y). Within the DAU (5) selection multiplexers (13,14) select full adder outputs to provide Y, or bit-select from adders and the input (X) to provide Y. For a radix-4 operation, MSBs are taken from the input (X), middle bits are taken from the output of a first adder (adder1), and the LSBs are taken from the output of a second adder (adder2) if there is a carry out from the first adder.