A synchronising circuit for a PBX for synchronising a PCM clock signal with basic rate ISDN network signals

A communications circuit (1) of a PBX comprises a control circuit (3) for controlling the circuit (1) and an interface circuit (4) which operated under the control of the control circuit (3) for receiving eight ISDN lines on inputs (1) to (8) of the interface circuit (4). Eight layer one integrated circuit chips (5) are provided, one for each ISDN line. Each layer one integrated circuit chips (5) are provided, one for each ISDN line. Each layer one integrated circuit chip (5) outputs a line synchronous clock signal which is derived from the basic rate ISDN network signal on the corresponding ISDN line. A synchronising circuit (2) comprises a digital phase locked loop circuit (IC 24) for providing synchronised PCM clock signals one of which is applied to an input (1) of a digital switch matrix (6) for clocking ISDN signals through the digital switch matrix (6). The phase locked loop circuit (IC 24) outputs the synchronised PCM clock signal which is divided in a digital counter (IC 23), (IC 30) and (IC 31) to appropriate frequencies. The synchronised PCM clock signal is fed back to the digital phase locked loop circuit (IC 24) where it is compared with one of the line synchronous clock signals which is selected by a multiplexer (IC 26). The two signals are compared in the digital phase locked loop circuit (IC 24) and single pulses at the same frequency as the synchronised PCM clock signal are added to or deleted from the synchronised PCM clock signal to push the signal into phase and phase lock the signal with the selected line synchronous clock signal. .