Secure integrated circuit chip with conductive shield

A chip includes a secure section 11 having a fuse element 56 and a fuse altering device 58. A predetermined data pattern is formed by wiring and inverters 62 connected between an erasable memory 52 and an AND gate 60. An enabling circuit 55 allows the predetermined data pattern to be written into the memory 52 when an appropriate control signal is received at a terminal 63. The state of the fuse element 56 is then irreversibly altered by the fuse altering device 58 so that the predetermined data pattern in the memory 52 cannot be changed. After final pressing and packaging, secure data may be stored in a secure memory M since the data pattern in the memory 52 is the same as that in the inverters 62. Once the secure data is stored, an erase signal is provided to terminal 66 which thereby erases the memory 52. The contents of the secure memory M are thereafter unalterable.