Electronic circuit design
An electronic circuit is designed to be ready for manufacture in a method (1) which involves generation of a HDL net list (2) to which pad stacks and gates are added (4). There is then design optimisation (5) using signal integrity simulation and timing analysis tools which is for modification circu...
Gespeichert in:
Hauptverfasser: | , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | An electronic circuit is designed to be ready for manufacture in a method (1) which involves generation of a HDL net list (2) to which pad stacks and gates are added (4). There is then design optimisation (5) using signal integrity simulation and timing analysis tools which is for modification circuit layout. The design is then routed (6) and there is final optimisation (7) with signal integrity simulation and timing analysis. |
---|