SUPERSCALAR MICROPROCESSOR INSTRUCTION PIPELINE INCLUDING INSTRUCTION DISPATCH AND RELEASE CONTROL

A multifunction superscalar microprocessor is equipped with a high-speed high-efficiency pipeline. The pipeline quickly responds to instructions dispatched from available sources within it. Exceptional conditions occurring in the pipeline are all processed efficiently by the same method at the same pipeline stage. Before processing to an instruction decoding stage, a fetched instruction is pre-decoded by attaching first and second regions. The first region contains information of the source of the fetched instruction, while the second region contains a source classification region for recognizing the kinds of sources used by instructions similar to the fetched one. The pre-decoded instruction is sent to the instruction decoding stage, and this instruction is dispatched. The dispatched instruction is delivered to a functional unit for processing according to the information in the first and second regions.