Improvements in or relating to electrical demodulators

795,196. Phase-sensitive circuits. SMITH & SONS (ENGLAND), Ltd., S. April 3, 1956 [April 1, 1955], No. 9548/55. Class 38 (4). In a demodulator for an amplitude modulated signal comprising a non-linear resistor the slope of the current/voltage characteristic of which is the same for a given magni...

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Hauptverfasser: BURROWS GEOFFREY HAROLD, GARDNER PETER ALAN EDWARD
Format: Patent
Sprache:eng
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Zusammenfassung:795,196. Phase-sensitive circuits. SMITH & SONS (ENGLAND), Ltd., S. April 3, 1956 [April 1, 1955], No. 9548/55. Class 38 (4). In a demodulator for an amplitude modulated signal comprising a non-linear resistor the slope of the current/voltage characteristic of which is the same for a given magnitude of voltage whatever its sign; the signal is connected to the load through the non-linear resistor to which is also applied a demodulator voltage source having a frequency equal to half that of the signal carrier. The non-linear resistor may comprise a pair of oppositely poled rectifiers in parallel, and backbiasing arrangements as described with reference to Fig. 3 (not shown) may be included. Reference source 6, Fig. 1, having a voltage large compared with the signal from source 1 is applied to a transformer 5 the secondary 4 of which has a centre tap connected to a load 7, and the signal v sin (2 pt + a) in passing through the non-linear resistors which have a conductance varying predominantly at twice the frequency of source 6, results in a direct current through load 7 which is dependent on the modulation of the signal and the phase of the carrier. Even harmonics of voltage 6 are removed by filtering and if resistor 3 and the corresponding half of secondary 4 are omitted it would be necessary to remove or compensate for a large component of source 6. An arrangement in which two reference sources equal in amplitude and in phase quadrature are employed to cancel harmonics in the output is described with reference to Fig. 2 (not shown) and further embodiments in which the rectifier bias is produced by a resistor-capacitor network are described with reference to Figs. 5 and 6 (not shown).