Hazard-checking in task delegation

An apparatus for data processing comprises a data processing pipeline, and extension processing circuitry (threadlet extension) to perform (802) a delegated task asynchronously to the data processing pipeline in response to a decoding circuitry decoding (800) an extension start instruction. The apparatus also comprises hazard detection circuitry to detect data hazards associated with processing operations performed by the data processing pipeline. When the data processing pipeline is in an extension hazard checking state (806), the presence of a hazard condition can be determined (808) in dependence on whether a given memory access, to be performed in response a given memory access instruction following the extension start instruction in program order, is for accessing an address which falls within a group of addresses anticipated to be accessed by the extension processing circuitry during performance of the delegated task. Progress indicators for addresses accessed by the extension circuitry during performance of the delegated task are used for detecting: read-after-write (RAW), write-after-write (WAW), write-after-read (WAR). Extension hazard checking moderating instruction may disable determining hazard conditions and enable determining of hazard condition for at least one type of memory access instruction. Delegated tasks relate to custom hardware functions: memcpy, memset, compression, encryption, string processing.