Selectively powered embedded memory systems and methods
A system comprises a memory block 200 that is selectively operated in a full power mode or a half power mode. The memory block comprises an input/output port 210, 220, a first sub-block 230 that is powered on during the full power mode and during the half power mode. and a second sub-block 260 that...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | A system comprises a memory block 200 that is selectively operated in a full power mode or a half power mode. The memory block comprises an input/output port 210, 220, a first sub-block 230 that is powered on during the full power mode and during the half power mode. and a second sub-block 260 that is powered on during the full power mode and powered off during the half power mode. Routing hardware 238,248,268,278 passes data between the input/output port 210,220 and the first and second sub-blocks 230,260. The routing hardware may pass data between the input/output port 210,220 and the sub-blocks 230,260 in full power mode and between the input/output port and only the first sub-block during the half power mode. In full power mode, the first and second sub-blocks may store data as words spanning both sub-blocks or as words contained separately in the sub-blocks, and as words contained only in the first sub-block in the half power mode. The system may be a programmable logic device (PLD) (100, figure 1) and the memory block 200 may be operated in full or half power mode according to configuration data stored in the PLD. |
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