Multi-port circuit architecture

A device comprising a multi-port circuit architecture with multiple ports port_0, port_1, ... port_8 (e.g. a multi-port register, MPR), wherein the multi-port circuit architecture expands a primary clock CLK into multiple dummy clocks CLK_Dummy_1, CLK_Dummy_2, ... CLK_Dummy_8. This arrangement enables the separate tracking, simulation and reporting, to a central processing unit (CPU), of clock power consumption for each port of the multiple ports. The expansion of the primary clock into multiple dummy clocks may be effected by shorting the primary clock with the multiple dummy clocks, for example via a conductive coupling feature 214 such as a conductive signal rail, a metal wire or similar. The device may comprise a primary port and multiple secondary ports. In that case, the primary clock may be applied to the primary port and the dummy clocks may be applied to respective secondary ports. Internal control logic may be used to separately report the internal clock power consumption for each port to the CPU, or shared control logic may be used to report the common clock power consumption for the primary port to the CPU.