Asynchronous SAR logic

A comparator circuit 100 of an asynchronous SAR ADC comprises a two-output comparator 101 arranged to receive first and second input signals 102 & 103, compare the input signals, and drive one of the first and second comparison signals 104 & 105 to a set state based on the comparison. A first bit output terminal 114 of the circuit 100 is in a set state when the first comparison signal 104 is in a set state. A second bit output terminal 115 of the circuit is in a set state when the second comparison signal 105 is in a set state. If a predetermined duration passes after the triggering 109 of the comparator and the first and second comparison signals 104 & 105 are both in the reset state, then control logic ends the comparison operation and establishes a set state at both the first and the second output terminals 114 & 115. In effect, the control logic overrides the comparator output and instead provides a defined output indicative of metastability. This allows metastability of the comparator to be detected.