Apparatus comprising interrupt tracking circuitry
A data processing system 18 comprises one or more processors 4, an interrupt controller 10 and shared memory 8 connected with an interconnect 6. The interrupt controller comprises interrupt detection circuitry 40 to detect interrupts. It also comprises interrupt tracking circuitry 48, which uses lin...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | A data processing system 18 comprises one or more processors 4, an interrupt controller 10 and shared memory 8 connected with an interconnect 6. The interrupt controller comprises interrupt detection circuitry 40 to detect interrupts. It also comprises interrupt tracking circuitry 48, which uses linked lists to track to track pending interrupts. The linked lists may be stored in one or more tables 20 in the shared memory. If multiple tables are used, the pointers may comprise a table identifier and an index into the table. Separate linked lists may be used for physical and virtual interrupts and for different priority levels. Different tables may be used for different classes of interrupt. The linked lists may be doubly linked lists with head and tail pointers. When an interrupt is no longer pending, it is removed from the list. |
---|