Interrupt controller, apparatus, interrupt control method and computer-readable medium

An interrupt controller controls signalling of a given interrupt having a given interrupt identifier to a target interrupt handling context, by controlling one or more memory write requests to be issued in accordance with a coherency protocol supported by a cache coherent interconnect, to maintain a set of memory-based interrupt tracking structures corresponding to the target interrupt handling context, including: a selected interrupt queue structure selected from among a plurality of interrupt queue structures based on the given interrupt identifier, to queue the given interrupt for processing by the target interrupt handling context; and a queue status summary structure to indicate which of the plurality of interrupt queue structures hold pending interrupts awaiting processing by the target interrupt handling context.