Neural network comprising matrix multiplication

Methods and data processing systems are disclosed for implementing one or more fully connected layers of a neural network in hardware.According to embodiments, coefficient data for at least one fully connected layer is loaded into an input buffer of a hardware accelerator, and input data for the at...

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Bibliographische Detailangaben
Hauptverfasser: James Imber, Biswarup Choudhury, Aria Ahmadi, Timothy Atherton, Cagatay Dikici
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:Methods and data processing systems are disclosed for implementing one or more fully connected layers of a neural network in hardware.According to embodiments, coefficient data for at least one fully connected layer is loaded into an input buffer of a hardware accelerator, and input data for the at least one fully connected layer is loaded into a coefficient buffer of the hardware accelerator.To be accompanied, when published, by Figure 9A of the accompanying drawings.