Time, space, and energy efficient neural inference via parallelism and on-chip memory

Time, space, and energy efficient neural inference via parallelism and on-chip memory

Neural inference chips and cores adapted to provide time, space, and energy efficient neural inference via parallelism and on-chip memory are provided. In various embodiments, the neural inference chips comprise: a plurality of neural cores interconnected by an on-chip network; a first on-chip memor...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Andrew Stephen Cassidy, Dharmendra Shantilal Modha, Pallab Datta, Hartmut Penner, Jennifer Klamo, Steven Kyle Esser, Rathinakumar Appuswamy, John Vernon` Arthur, Jun Sawada, Brian Seisho Taba, Myron Dale Flickner
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:Neural inference chips and cores adapted to provide time, space, and energy efficient neural inference via parallelism and on-chip memory are provided. In various embodiments, the neural inference chips comprise: a plurality of neural cores interconnected by an on-chip network; a first on-chip memory for storing a neural network model, the first on-chip memory being connected to each of the plurality of cores by the on-chip network; a second on-chip memory for storing input and output data, the second on-chip memory being connected to each of the plurality of cores by the on-chip network.