Instruction and logic to provide vector scatter-op and gather-op functionality

Decoding an SIMD instruction comprising a first operation and a scatter operation. The SIMD instruction is to indicate a first source register with a first plurality of data elements, indicate a second source register comprising a second plurality of data element different from the first, and indicate a third source register which has a plurality of indices, each corresponding to the first plurality of elements. Also included is or more execution units to perform the first operation on the first and second data elements to form corresponding result data elements, and then perform a scatter operation to store each result data element in memory. The first operation may be binary, addition, multiplication or ternary. The first source register may comprise 512 bits and wherein the data elements of the first source register are one of 32 bit data elements and 64 bit data elements.