Error detection within an integrated circuit chip

Error detection within an integrated circuit chip, particularly a system on chip (SOC), is performed by analysing transactions communicated over interconnect circuitry 210 on the integrated circuit chip to detect whether a message contains a data error. A memory 214 of the integrated circuit chip is coupled to the interconnect circuitry and is tested by a scanning unit 310 to detect whether there is a data error stored in the memory. In response to detecting a data error in a transaction and/or the memory, an action indicative of a data error is performed e.g. error correction or alert generation. The memory may be checked using a hashing unit 314 and the transactions may be checked using parity or cyclic redundancy checking (CRC). Error data may be analysed by a profile unit 308. The memory may only be scanned when the interconnect is free from other transactions at times determined by the error profile.