An apparatus and method for controlling use of a register cache

An apparatus and method are provided for controlling use of a register cache. The apparatus has decode circuitry for decoding instructions retrieved from memory, execution circuitry to execute the decoded instructions in order to perform operations on data values, and a register file having a plurality of registers for storing the data values to be operated on by the execution circuitry. Further, a register cache is provided that comprises a plurality of entries, and is arranged to cache a subset of the data values. Each entry is arranged to cache a data value and an indication of the register associated with that cached data value. Prefetch circuitry is then used to prefetch data values from the register file into the register cache. Further, operand analysis circuitry derives source operand information for an instruction fetched from memory, at least prior to the decode circuitry completing decoding of that instruction. It then causes provision to the prefetch circuitry of at least one register identifier determined from the source operand information. The prefetch circuitry then utilises that at least one register identifier when determining which data values to prefetch into the register cache. Such an approach can significantly increase the hit rate within the register cache, hence improving performance.