A direct coupled biasing circuit for high frequency applications

Amplifier (e.g RF or microwave amplifier to drive antenna) comprises an adjustable biasing voltage coupled through a parallel LC load (tank L1) to the output of a first stage (transistor MOSFET N2), which is directly coupled to an input of a second or final (next) stage (transistor MOSFET N3), and w...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Khong-Meng Tham, Zaw Soe
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:Amplifier (e.g RF or microwave amplifier to drive antenna) comprises an adjustable biasing voltage coupled through a parallel LC load (tank L1) to the output of a first stage (transistor MOSFET N2), which is directly coupled to an input of a second or final (next) stage (transistor MOSFET N3), and whereby at least one characteristic such as quiescent or bias current of second stage N3 is controlled by adjustment of the biasing voltage. This circuit may comprise a reference transistor N1 which is a scaled version of the second or final stage transistor N3. An adjustable current source I4, (or switchable scaled reference transistors of width Wa,Wb,Wc figure 2b) may provide the adjustable reference bias voltage whereby the reference transistor N1 is driven in saturation. The second or final stage transistor may also have a second parallel LC circuit L2 coupling the supply VDD to its output. An input signal Vin on the first stage input (transistor N2) may pass to the output of the first stage 1-6 forming an intermediate signal which is directly coupled to the second stage input (transistor N3). Alternatively a control loop (e.g unity gain operational amplifier) may monitor a biasing voltage to generate an adjustable biasing voltage fed to the parallel LC load L1. Direct coupling, for example with a metallic trace, eliminates the need for capacitor or transformer coupling and undesirable parasitic capacitance/inductance effects in 60GHz microwave circuits, where interstate distances must be minimized. This approach is also economic in terms of IC die area. A method of use is also included.