Electrical isolation in photonic integrated circuits

Electrical isolation between subsections in a waveguide structure for a photonic integrated device (PIC). The structure comprises a substrate, a buffer layer 107 ( Figure 1) and a core layer 105 (Figure 1), the buffer layer being located between the substrate 108 (Figure 1) and the core and comprising a dopant of a first type, the first type being either n-type or p- type. Prior to adding any layer to a side of the core layer opposite to the buffer layer at least one area may be selected to be an electrical isolation region 401. A dielectric mask may be applied to a surface of the core layer opposite to the buffer layer 402, with a window in the mask exposing an area of the surface corresponding to the selected electrical isolation region 403, implementing diffusion of a dopant of a second type, the second type being of opposite polarity to the first type, and allowing the dopant of the second type to penetrate to the substrate to form a blocking junction 404.