Layered vertical field effect transistor and methods of fabrication

A III-nitride vertical field effect transistor (FET) comprises a base plate 1, a mask layer 6 on the base plate having openings for exposure of the base plate; a drain 2 grown epitaxially onto regions of the base plate exposed by the openings of the mask layer; an insulation layer 3 grown epitaxially onto the drain; a source 4 grown epitaxially onto the insulation layer; a vertical nitride stack 5 grown epitaxially onto the side faces of the drain, the insulation layer and the source, and overlaying the mask layer; the stack provides a vertical conducting channel to connect the source to the drain. A current flowing from the source to the drain through the conducting channel can be modulated by an electrical voltage that is applied to the side face of the vertical nitride stack. There are preferably also electrodes 7, 8, 10 and edge terms 9. The drain may grow partly over the mask layer i.e. there may be epitaxial lateral overgrowth (ELOG). A double width mask may be used. A method for reducing the gate length is also claimed.