Register renaming

An apparatus has decoding circuitry to decode instructions to generate micro-operations, and register rename circuitry to map architectural register specifiers specified by the instructions to physical registers to be accessed in response to the micro-operations. In response to an instruction specifying a selected architectural register specifier as both a source register and a destination register, for which the decoding circuitry is to generate two or more micro-operations, the register rename circuitry stores an indication of a physical register previously mapped to said selected architectural register specifier. In response to one of the micro-operations for which the source register corresponds to the selected architectural register specifier and which follows a micro-operation for which the destination register corresponds to the selected architectural register specifier, the register rename circuitry maps the selected architectural register specifier to the physical register indicated by the stored indication.