Enforcing data protection in an interconnect

Disclosed is interconnect circuitry that couples master devices, each with a local cache, to a memory. The interconnect has transaction circuitry, that when it receives a memory transaction from a first master device, the transaction specifying a target and a coherency type, causes a snoop access to be transmitted to a cache of a second master device depending on the coherency type. When a memory transaction is received from the second master device in order to maintain coherency of a copy of the target in the cache, the transaction circuitry transmits the transaction to a memory protection controller which polices access to the memory. The interconnect circuitry also has transaction monitoring circuitry that when the transaction is received from the first device modifies the coherency type to a memory accessing coherency type. The transaction coherency circuitry based on the memory accessing coherency type initiates an access to the target in the memory when a modified version of the of the copy of the target is in the cache.