Read level grouping for increased flash performance
A computer implemented method 1400 (and a data storage system such as a Solid State Disc (SSD) consisting of a plurality of Multi-Level Cell (MLC) NAND FLASH memory devices, and a controller coupled to the flash memory) the method comprising of reading a first sample of wordlines in a particular blo...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | A computer implemented method 1400 (and a data storage system such as a Solid State Disc (SSD) consisting of a plurality of Multi-Level Cell (MLC) NAND FLASH memory devices, and a controller coupled to the flash memory) the method comprising of reading a first sample of wordlines in a particular block of memory 1402, each associated with a wordline identifier (or address), and to be read multiple times at different read level voltages to produce an associated error count, and generating a read table of error counts 1402 to store an error count for each combination of wordline and respective read level voltage used to read the wordlines. A plurality of wordline groups 1404 are generated based on the table of error counts, with each group associating a different read level offset voltage (bias voltage) with a plurality of wordline addresses. The storage device is configured to read memory cells using a read level offset voltage of a generated offset wordline group associated with a wordline address of the memory cells to be read 1406. After a predetermined point in a life cycle of a respective memory block, the table is regenerated and plurality of offset wordline groups are regenerated based the regenerated table of error counts 1408, 1410. A plurality of wordline groups may be based on the wordline identifiers (or addresses) used to index the table of error counts, the groups, for the purpose of reading, associating a different read level with a plurality of wordlines. The wordline groups may be based on an initial division of wordlines corresponding to the wordline identifiers each group comprising of a consecutively grouped portion of the corresponding wordlines pairs with a corresponding read level voltage, whilst the pairing are selected for an overall lowest possible error count. The table of error counts may be regenerated after a certain point in a life cycle of a memory block, using a second sample of wordlines, and based on for example reaching a pre-set number of program/erase cycles 1410. Using log likelihood LLR methodology, the regeneration of error count tables may include generating a plurality of reliability values (both negative and positive) and identifying a calibrated voltage corresponding to the zero crossing point for the second sample of wordlines. |
---|