A method of generating a layout of an integrated circuit comprising both standard cells and at least one memory instance

A method and computer program for generating a layout of an integrated circuit (IC) incorporating both standard cells defining functional components and at least one memory instance generated by a memory compiler to define a memory device of the integrated circuit (500 figure 10). The memory compiler 325 is provided with a memory architecture specifying a definition of circuit elements and data defining rules for combining those circuit elements in order to generate memory instances conforming to the memory architecture. Input data is received specifying one or more properties 310 of a desired memory instance. The memory compiler 325 is then used to generate the desired memory instance based on the input data 310 and using the specified memory architecture. A standard cell library 315 is provided, with each standard cell within the standard cell library defining a corresponding functional component. In an integration enhancement mode of operation 320, the memory compiler references at least one property of the standard cell library 325 in order to generate the desired memory instance in a form that will reduce an area overhead associated with a boundary between that desired memory instance and surrounding standard cells when that desired memory instance is integrated into the layout (figure 6B). The layout is then generated by populating standard cell rows with standard cells 315 selected from the standard cell library in order to provide the functional components required by the integrated circuit, and integrating into the layout the desired memory instance provided by the memory compiler. A place and route algorithm 335 is used to generate the layout of the IC 340, 345. The invention provides an area efficient mechanism for generating the layout of an IC.