Ethernet link incorporating forward error correction

A method of FEC encoding, particularly for 1Gb/s Ethernet point-to-point links, in which the FEC parity symbols 13 are interspersed in the packet data of packet 12. For this purpose the packet delimiters may be used as FEC block markers. Due to the interspersed nature of the FEC data which is includ...

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Bibliographische Detailangaben
Hauptverfasser: ANNE GERALDINE O'CONNELL, CON CREMIN
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:A method of FEC encoding, particularly for 1Gb/s Ethernet point-to-point links, in which the FEC parity symbols 13 are interspersed in the packet data of packet 12. For this purpose the packet delimiters may be used as FEC block markers. Due to the interspersed nature of the FEC data which is included for each segment after each segment the arrangement allows the use of a low latency FEC block. The arrangement employs rate gearing to avoid degradation of the data throughput such that the stream is transmitted at a second rate, marginally higher than the rate the stream is received by the transmitter, so that the rate of the stream transmitted with the FEC (parity) data included is equivalent to the rate of the stream without the parity data received/input at the marginally lower rate. The rate gearing may be facilitated by rate-changing FIFOs at the transmitter and receiver. The parity data may be Reed Solomon symbols. Auto-negotiation of the capability to support the FEC encoding may also be used by the transmitter and receiver. The abstract Figure shows a packet according to the preferred embodiment 12 with interspersed FEC (parity) symbols compared to a prior art arrangement 10.