Memory protection

An integrated-circuit device 1 comprises a processor 7, non-volatile memory 13, non-volatile memory control logic 20, and memory protection logic 9. The memory protection logic 9 is arranged to control access to a protectable region of the non volatile memory 13 in dependence on protection configuration data stored in a protection-configuration region of the non-volatile memory. The device 1 is arranged to store, in the protection-configuration region, one or more values that define the protectable region or that define a protectable region of volatile memory. The non-volatile memory control logic 20 is arranged to prevent writing to any portion of the protection-configuration region unless that portion is in an erased state. The non-volatile memory control logic 20 is further arranged to allow the protection-configuration region to be erased only if the protectable region is in an erased state. The protectable region of non-volatile memory or volatile memory may be variable and defined by one or more addresses stored in the protection-configuration region.