SRAM array comprising multiple cell cores

An SRAM array 100 comprising multiple cell cores 102, 104, 106, 108 to store and retrieve data, each cell core comprising a plurality of SRAM cells 112, and wherein at least two corresponding cell cores 102, 104 and 106, 108 build a cell core row 122. A word decoder 110 configured to decode incoming address signals 116 representing a storage address into a single word line 114, so that one storage word is activated. The word decoder 110 comprises, a cell core select unit (306, figure 3) configured to generate a cell core row select signal (402, figure 4) from a combination of a first part (412) of the incoming address signals 116 and a received clock signal (308, figure 4), a decoding element (302, 304, figure 4) for each cell core row 122, the decoding element comprising a first decoding block (404, figure 4) for decoding a second part (414, figure 4) of the incoming address signals 116 for building an upper portion (408) of word line select signals (422) and a second decoding block (406 figure 4) for decoding a third part (416) of the incoming address signals 116 for building a lower portion (410, figure 4) of word line select signals (422), a word line driver (418, 420) for each cell core row (122) configured to combine the upper portion (408) of the word line select signal (422) from the first decoding block (404) and the lower portion (410) of the word line select signal (422) from the second decoding block (406) to form a unique word line signal 114 per storage address.