Fail safe circuit
A fail safe apparatus 10 prevents output of a signal to an inverter 11 in the event of a fault to prevent operation of a motor 15. The apparatus 10 comprises a signal control unit 4 having a signal buffering unit 42, 44. The signal buffering unit 42, 44 receives an input signal and passes the input...
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Format: | Patent |
Sprache: | eng |
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Zusammenfassung: | A fail safe apparatus 10 prevents output of a signal to an inverter 11 in the event of a fault to prevent operation of a motor 15. The apparatus 10 comprises a signal control unit 4 having a signal buffering unit 42, 44. The signal buffering unit 42, 44 receives an input signal and passes the input signal to the output only when the signal buffering unit 42, 44 is powered. The negative power supply terminal of the signal buffering unit is supplied by a first power source (8, figure 1). The positive power supply terminal is supplied by a boost circuit (9) arranged to boost the voltage of the first power source (8) to a boosted voltage higher than the voltage of the first power source (8). The signal buffering unit 42, 44 is powered only when the boosted voltage is supplied to the positive power supply terminal. An apparatus for providing output voltages for driving a motor has a first switching arrangement powered by a first power supply, a second switching arrangement, and a power storage arrangement. The power storage arrangement is charged by the first power supply when the first switching arrangement is supplying output, and supplies power to the second switching arrangement when the second switching arrangement is supplying output. A control unit may prevent supply of both outputs by preventing supply of control signals to the first switching arrangement. |
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