System for electrical testing and manufacturing a 3D chip stack and method

A method for electrical testing of a 3D integrated circuit chip stack is described. The 3D integrated circuit chip stack comprises at least a first integrated circuit chip (300) and a second integrated circuit chip (400). The first integrated circuit chip (300) and the second integrated circuit chip...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: QUINTINO LORENZO TRIANNI, ECKHARD KUNIGKEIT, MARTIN ECKERT, OTTO ANDREAS TORREITER
Format: Patent
Sprache:eng
Schlagworte:
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