System for electrical testing and manufacturing a 3D chip stack and method

A method for electrical testing of a 3D integrated circuit chip stack is described. The 3D integrated circuit chip stack comprises at least a first integrated circuit chip (300) and a second integrated circuit chip (400). The first integrated circuit chip (300) and the second integrated circuit chip...

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Bibliographische Detailangaben
Hauptverfasser:	QUINTINO LORENZO TRIANNI, ECKHARD KUNIGKEIT, MARTIN ECKERT, OTTO ANDREAS TORREITER
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS PRINTED CIRCUITS SEMICONDUCTOR DEVICES TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION TECHNICAL SUBJECTS COVERED BY FORMER USPC TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS TESTING
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Beschreibung
Zusammenfassung:	A method for electrical testing of a 3D integrated circuit chip stack is described. The 3D integrated circuit chip stack comprises at least a first integrated circuit chip (300) and a second integrated circuit chip (400). The first integrated circuit chip (300) and the second integrated circuit chip (400) are not soldered together for performing electrical testing. The testing improves yield by allowing defective chips to be found prior to soldering of the chip to the IC chip stack. The assembly for holding the IC chips during testing comprises holes 220 in its sidewalls which allow a vacuum to be formed between the chips, creating a mechanical connection between the chips.