Method and apparatus for injecting errors into memory

Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address registe...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Theodros Yigzaw, Gopikrishna Jandhyala, Jose A Vargas, Mohan J Kumar, Kai Cheng
Format: Patent
Sprache:eng
Schlagworte:
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Beschreibung
Zusammenfassung:Disclosed is an apparatus and a method to inject errors to a memory. In one embodiment, a dedicated interface includes an error injection system address register and an error injection mask register coupled to the error injection system address register. If the error injection system address register includes a system address that matches an incoming write address, the error injection mask register outputs an error to the memory.